? semiconductor components industries, llc, 2012 january, 2012 ? rev. 1 1 publication order number: p1p3800a/d p1p3800a phase synchronizing clock generator product description p1p3800a is a phase synchronizing clock generator that generates four outputs from an input clock. output frequency will be a divide by two of the input clock. the phase of the output clocks is selectable through four select signals s1, s2, s3 and s4. refer to output clock selection table . the outputs will go ?low? when all the select signals are ?low?. the transition to a new state of the output will be ?glitch free? when the select inputs change state. a power down signal enables the device to be driven to a power save mode, when active. the device works over a supply voltage range of 3.8 v ? 5.5 v. the device is available in a 12 ? lead 3mmx3mm wqfn package and operates over -40 c to +85 c. features ? input clock frequency: 120 hz ? 240 hz (external reference clock) ? output clock frequency: 60 hz ? 120 hz ? 4 clock outputs ? 4 two level controls to select sets of clock outputs ? output buffer drive strength: 8 ma ? supply voltage: 3.8 v ? 5.5 v ? power down for power save ? 12 ? lead 3mmx3mm wqfn package ? operating temperature range: -40 c to +85 c ? these devices are pb ? free, halogen free/bfr free and are rohs compliant application ? p1p3800a can be used in applications where phase synchronization is needed. v dd gnd clkin digital logic & divider s [1:4] pd# clkout [1:4] figure 1. block diagram wqfn12 case 510ah marking diagram http://onsemi.com pd# clkout4 clkout3 s1 clkin s2 pin configuration see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information a = assembly location l = wafer lot y = year w = work week = pb ? free package p1p 3800a alyw 12 11 10 9 56 7 4 8 3 clkout2 1 2 1 s4 gnd s3 v clkout1 (note: microdot may be in either location) p1p3800a (top ? view) dd
p1p3800a http://onsemi.com 2 table 1. pin description pin# pin name type description 1 s2 i output clock select. refer output clock selection table. has no default state 2 s1 i output clock select. refer output clock selection table. has no default state. 3 clkin i external reference clock input 4 s3 i output clock select. refer output clock selection table. has no default state. 5 gnd p ground to entire chip 6 s4 i output clock select. refer output clock selection table. has no default state. 7 clkout3 o buffered clock output. refer clkout diagram 8 clkout4 o buffered clock output. refer clkout diagram 9 pd# i power down. powers down the entire chip when pulled low. clkout [1:4] will be low when power down is enabled. has no default state. 10 clkout2 o buffered clock output. refer clkout diagram 11 v dd p supply voltage 12 clkout1 o buffered clock output. refer clkout diagram table 2. output clock selection table s4 s3 s2 s1 clkout4 clkout3 clkout2 clkout1 0 0 0 0 low low low low 0 0 0 1 clk# clk# clk# clk 0 0 1 0 clk# clk# clk clk# 0 0 1 1 clk# clk# clk clk 0 1 0 0 clk# clk clk# clk# 0 1 0 1 clk# clk clk# clk 0 1 1 0 clk# clk clk clk# 0 1 1 1 clk# clk clk clk 1 0 0 0 clk clk# clk# clk# 1 0 0 1 clk clk# clk# clk 1 0 1 0 clk clk# clk clk# 1 0 1 1 clk clk# clk clk 1 1 0 0 clk clk clk# clk# 1 1 0 1 clk clk clk# clk 1 1 1 0 clk clk clk clk# 1 1 1 1 clk clk clk clk
p1p3800a http://onsemi.com 3 clkout diagram low clk# clk timing diagram for glitch free operation (for reference) (transition of outputs from any state to any other state) s4=1, s3=1, s2=1, s1=0 change area s4=1, s3=1, s2=0, s1=1 change area s4=0, s3=0, s2=1, s1=1 pd# pd#=0 latency latency input clock clkout1 clkout2 clkout3 clkout4 note: transition to new state will happen after a latency of one output clock cycle after completing the present output clock cycle transition to new state will happen after a latency of up to 3 input clock cycles excluding the input cycle where the transit ion has occured. power up v dd clkout i/p clk s1~s4 in any stable state valid clock according to s1~s4 10 s(min) note: transition to new state will happen after a latency of up to 2 input clock cycles excluding the input cycle where the transition has occured.
p1p3800a http://onsemi.com 4 pd# operation valid clock according to s1~s4 10 s(min) pd# i/p clk s1~s4 in any stable state clkout note: transition to new state will happen after a latency of up to 2 input clock cycles excluding the input cycle where the transition has occured.
p1p3800a http://onsemi.com 5 table 3. operating conditions symbol parameter min max unit v dd supply voltage 3.8 5.5 v t a operating temperature ? 40 +85 c c l load capacitance 15 pf c in input capacitance 7.0 pf table 4. absolute maximum ratings symbol parameter rating unit v dd voltage on v dd pin with respect to ground ? 0.5 to +7.0 v v in voltage on any input pin with respect to ground ? 0.5 to +4.0 v t stg storage temperature ? 65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22 ? a114 ? b) 2.0 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. table 5. dc electrical characteristics symbol parameter min typ max unit v dd operating voltage 3.8 5.0 5.5 v v il input low voltage (note 1) gnd ? 0.3 0.8 v v ih input high voltage (note 1) 1.6 3.0 v i il input low current 10 a i ih input high current 10 a v ol output low voltage i ol = 8 ma 0.4 v v oh output high voltage i oh = ? 8 ma v dd ? 0.6* v i cc power down current (pd# pulled to gnd) 1.0 a i dd **dynamic supply current, pd# = 5.5 v; s[1:4] = 5.5 v/gnd; clkin swing = 0 to 5.5 v; v dd = 5.5 v 1.8 ma dynamic supply current, pd# = 3 v; s[1:4] = 3 v/gnd; clkin swing = 0 to 3.0 v 3.0 dynamic supply current, pd# = 3 v; s[1:4] = 1.6 v; clkin swing = 0 to 1.6 v 4.0 dynamic supply current, pd# = s[1:4] = 1.6 v; clkin swing = 0 to 1.6 v 5.0 *for v dd = 5 v, v oh = v dd ? 0.4 v. **indicative value, not a recommended operating condition. 1. parameter is guaranteed by design and characterization. not tested in production.
p1p3800a http://onsemi.com 6 table 6. ac electrical characteristics symbol parameter min typ max unit clkin input clock frequency 120 240 hz clkout output clock frequency 60 120 hz t lh , t hl output rise / fall time (measured from 20% to 80%) (notes 1, 2) 10 s t lh , t hl input rise / fall time (measured from 20% to 80%) 50 s t dout output duty cycle (measured at v dd /2) (notes 1, 2) 49 50 51 % t din input duty cycle 49 50 51 % t su set up time for control signals, s[1:4], pd# to input clock rising edge (note 1) 60 s t h hold up time for control signals, s[1:4], pd# to input clock rising edge (note 1) 60 s t skew output ? output clock skew (note 1) 10 s 2. all parameters are specified with 15 pf loaded output. typical i dd vs pd# input voltage plot ordering information part number package shipping ? p1p3800ag12crtwg 12 pin (3 mm x 3 mm) wqfn 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
p1p3800a http://onsemi.com 7 package dimensions wqfn12 3x3, 0.5p case 510ah issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? ??? a d e b c 0.10 pin one 2x reference 2x top view side view bottom view l d2 e2 c c 0.10 c 0.10 c 0.10 a1 seating plane e 12x note 3 b 12x 0.10 c 0.05 c a b b dim min max millimeters a 0.65 0.85 a1 0.00 0.05 b 0.20 0.30 d 3.00 bsc d2 1.30 1.50 e 3.00 bsc e2 1.30 1.50 e 0.50 bsc k 0.20 ??? l 0.30 0.50 4 7 1 12 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2x 0.50 pitch 1.50 3.30 1 k dimensions: millimeters 0.63 12x note 4 2x 0.30 12x detail a a3 0.22 ref 13x a3 a detail b l1 detail a l alternate constructions ?? ?? ??? 0.00 0.15 outline package on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p1p3800a/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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